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CY62256
256K (32K x 8) Static RAM
Features
* High speed: 55 ns and 70 ns * Voltage range: 4.5V-5.5V operation * Low active power (70 ns, LL version) -- 275 mW (max.) * Low standby power (70 ns, LL version) -- 28 W (max.) * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power * Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packages
Functional Description[1]
The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER
I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5
512 x 512 ARRA Y
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05248 Rev. *B
*
3901 North First Street
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San Jose
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CA 95134 * 408-943-2600 Revised August 27, 2002
CY62256
Pin Configurations
OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
22 23 24 25 26 27 28 1 2 3 4 5 6 7 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16
Narrow SOIC Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND
DIP Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
TSOP I Top View (not to scale)
15 14 13 12 11 10 9 8 8 9 10 11 12 13 14 15 16 17 18 19 20 21
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
TSOP I Reverse Pinout Top View (not to scale)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied................................................... 0C to +70C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V
DC Input Voltage[2] ................................ -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
CY62256-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current GND < VI < VCC VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Output Leakage Current GND < VO < VCC, Output Disabled L LL ISB1 Automatic CE Max. VCC, CE > VIH, Power-down Current-- VIN > VIH or VIN < VIL, f = fMAX L TTL Inputs LL Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.5 -0.5 -0.5 28 25 25 0.5 0.4 0.3 Min. Typ.[3] 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 55 50 50 2 0.6 0.5 2.2 -0.5 -0.5 -0.5 28 25 25 0.5 0.4 0.3 Max. 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 55 50 50 2 0.6 0.5 CY62256-70 Min. Typ.[3] Max. Unit V V V V A A mA mA mA mA mA mA
Notes: 2. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 38-05248 Rev. *B
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CY62256
Electrical Characteristics Over the Operating Range (continued)
CY62256-55 Parameter ISB2 Description Test Conditions L LL LL Min. Typ.[3] 1 2 0.1 0.1 Max. 5 50 5 10 Automatic CE Max. VCC, CE > VCC - 0.3V Power-down Current-- VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 CMOS Inputs Indust'l Temp Range CY62256-70 Min. Typ.[3] 1 2 0.1 0.1 Max. 5 50 5 10 Unit mA A A A
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 6 8 Unit pF pF
AC Test Loads and Waveforms
R1 1800 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE Equivalent to: R2 990 3.0V 10% GND < 5 ns R1 1800 ALL INPUT PULSES 90% 90% 10% < 5 ns
(a)
(b)
THE VENIN EQUIVALENT 639 OUTPUT 1.77V
Data Retention Characteristics
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current L LL LL Ind'l tCDR[4] tR[4] Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC VCC = 3.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V Conditions[5] Min. 2.0 2 0.1 0.1 50 5 10 Typ.[3] Max. Unit V A A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. No input may exceed VCC + 0.5V.
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CY62256
Switching Characteristics Over the Operating Range[6]
CY62256-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[9, 10] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to WE HIGH to High-Z[7, 8] Low-Z[7] 5 55 45 45 0 0 40 25 0 20 5 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to CE LOW to CE HIGH to Low-Z[7] Low-Z[7] High-Z[7, 8] 0 55 5 20 5 20 0 70 5 25 OE HIGH to High-Z[7, 8] 5 55 25 5 25 55 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CY62256-70 Min. Max. Unit
CE LOW to Power-up CE HIGH to Power-down
Switching Waveforms
Read Cycle No. 1 [11, 12]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for Read cycle.
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CY62256
Switching Waveforms (continued)
Read Cycle No. 2 [12, 13]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB tHZOE tHZCE DATA VALID tRC
HIGH IMPEDANCE
DATA OUT
[9, 14, 15]
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 16 tHZOE
[9, 14, 15]
tHD
DATAIN VALID
Write Cycle No. 2 (CE Controlled)
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAIN VALID tHD tHA tSCE
Notes: 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05248 Rev. *B
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CY62256
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[10, 15]
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O NOTE 16 tHZWE
Note: 16. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAIN VALID tLZWE
Document #: 38-05248 Rev. *B
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CY62256
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4
SB
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4 1.2 NORMALIZED I CC ICC 3.0 2.5 2.0 ISB2 A 1.5 1.0 0.5 0.0 25 125 -0.5
STANDBY CURRENT vs. AMBIENT TEMPERATURE
1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25C ICC
NORMALIZED ICC, I
1.0 0.8 0.6 0.4 0.2 0.0 VCC =5.0V VIN =5.0V
ISB
VCC =5.0V VIN =5.0V 25 105
-55
-55
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA
AA
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 VCC =5.0V 0.8 0.6
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0
-55
25
125
SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA)
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
OUTPUT SINK CURRENT (mA)
NORMALIZED t
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
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CY62256
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 DELTA tAA (ns)
PO
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 VCC =4.5V TA =25C 1.25
NORMALIZED I CC vs.CYCLE TIME
2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0
NORMALIZED I
1.00
VCC =5.0V TA =25C VIN =0.5V
0.75
0.0
0
200
400
600
800 1000
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Read Write Deselect, Output Disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 70 Ordering Code CY62256LL-55SNI CY62256LL-55ZI CY62256-70SNC CY62256L-70SNC CY62256LL-70SNC CY62256L-70SNI CY62256LL-70SNI CY62256LL-70ZC CY62256LL-70ZI CY62256-70PC CY62256L-70PC CY62256LL-70PC CY62256LL-70ZRI Z28 Z28 P15 P15 P15 ZR28 28-lead Reverse Thin Small Outline Package Industrial 28-lead (600-Mil) Molded DIP 28-lead Thin Small Outline Package Commercial Industrial Commercial Industrial Package Name SN28 Z28 SN28 Package Type 28-lead (300-Mil Narrow Body) Narrow SOIC 28-lead Thin Small Outline Package 28-lead (300-Mil Narrow Body) Narrow SOIC Commercial Operating Range Industrial
Document #: 38-05248 Rev. *B
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CY62256
Package Diagrams
28-lead (600-mil) Molded DIP P15
51-85017-A
28-lead (300-mil) SNC (Narrow Body) SN28
51-85092-*B
Document #: 38-05248 Rev. *B
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CY62256
Package Diagrams (continued)
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28
51-85071-*G
28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05248 Rev. *B Page 10 of 11
(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62256
Document Title: CY62256 256K (32K x 8) Static RAM Document Number: 38-05248 REV. ** *A *B ECN NO. 113454 115227 116506 Issue Date 03/06/02 05/23/02 09/04/02 Orig. of Change MGN GBI GBI Description of Change Change from Spec number: 38-00455 to 38-05248 Remove obsolete parts from ordering info, standardize format Changed SN Package Diagram Added footnote 1. Corrected package description in Ordering Information table
Document #: 38-05248 Rev. *B
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